This invention generally relates to a large scale semiconductor logic device and more specifically to a clock signal circuit suitably used in a large scale semiconductor logic device for use in a high speed digital processing device.
A large scale semiconductor logic device having a large number of gates as many as 100000 gates generally includes, over a large area on the chip, many sequential logic circuits such as flip-flops, memories, register files, etc. These sequential logic circuits are operated in synchronism with plural clock signals having different phases which are applied to the circuits. These sequential circuits are hereinafter referred to as load circuits since they serve as loads when viewed from a clock signal source. Many lines for supplying the clock signals to the load circuits, which are arranged on the chip, are increasingly complicated as the logic device is large-scaled.
The logic device thus obtained is not properly operated if the above multi-phase clock signals are not coincident in their phase relation between when they are input to the logic device and when they reach the load circuits. Therefore, it is very important for the large scale semiconductor circuit that the multi-phase clock signals can be delivered to the load circuits with their less possible skew.
JP-A No. 55-80131 that was filed in Japan on Dec. 14, 1978 by Fujitsu Limited discloses means for producing clock pulses at a high speed and adjusting their phase which are carried out through the waveform conversion by a chopper circuit, and also proposes equivalent-length wiring for delivering the clock pulses with equal delay times.
However, it is increasingly difficult to make uniform the delay times in the respective clock signal lines with an increase of the integration degree of the circuits on the chip. It is also difficult to reduce the skew only by means of the equivalent-length wiring. A different number of the load circuits connected with a certain clock signal line will provide a different load capacitance, thus also providing a different delay time.